This invention relates to circuits using MOS or insulated gate field effect transistors, and more particularly to circuits for generating clock waveforms.
Semiconductor memory devices such as the widely used 4K, 16K or 64K dynamic MOS RAMs employ a large number of clock voltages which are generated on the chip itself. An external clock such as a chip enable clock or a row or column address stroke is used to initiate a series of internal clocks which have a wide variety of different delay times. In some cases, as many as twenty to twenty-five internal clocks are needed for the circuitry in a dynamic RAM chip. The delay periods must be precise, and the rise and/or fall rates correct. The output level usually needs to be a full supply level rather than a threshold lower than the supply voltage, and often the clock must drive a rather large capacitive load. Power dissipation is always a factor since the dissipation of the chip must be kept to a minimum, particularly when standby operation is provided.
It is the principal object of this invention to provide an improved clock voltage generator for a semiconductor device. Another object is to provide a clock generator for an MOS integrated circuit which exhibits a minimum power dissipation.